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S6A0031
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
June. 1999. Ver. 0.5
Prepared by:
Tae-Kwang, Park parktk@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6A0031 Specification Revision History Version 0.0 0.1 Original ECKON pad added POR circuit added Page 6: E_RD signal description is changed 0.2 E_RD: Active low signal for writing command in 6800 mode or high enable signal for reading command in 8080 mode. E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode, low enable signal for reading command in 8080 mode. Page 6: LCD DRIVER OUTPUT added 0.3 Page 18: Power ON / OFF timing added Page 29: IDD1 (VDD = 2.4~3.6V): 150A 50A Page 30: IDD1 (VDD = 3.6~5.5V): 250A 80A 0.4 Page 1, 2, 11: CGROM character size is changed from 256 to 254. Page 6: RW_WR active low -> active high Page 6: RW_WR active low -> low enable Page 20: Wait for more than 1.2us or Busy Check -> delete " or Busy Check" Page 21: Wait for more than 1.2us or Busy Check -> delete " or Busy Check" Jun.1999 May.1999 Apr.1999 Content Date Feb.1999 Mar.1999
0.5
Jun.1999
S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION.......................................................................................................................................... 1 FEATURES ................................................................................................................................................. 1 BLOCK DIAGRAM ...................................................................................................................................... 2 PAD CONFIGURATION............................................................................................................................... 3 PAD CENTER COORDINATES ................................................................................................................... 4 PIN DESCRIPTION...................................................................................................................................... 5 POWER SUPPLY ................................................................................................................................. 5 SYSTEM CONTROL............................................................................................................................. 5 MPU INTERFACE ................................................................................................................................ 6 LCD DRIVER OUTPUT......................................................................................................................... 6 TEST .................................................................................................................................................... 6 FUNCTIONAL DESCRIPTION ..................................................................................................................... 7 MICROPROCESSOR INTERFACE ...................................................................................................... 7 ADDRESS COUNTER (AC)................................................................................................................ 10 DISPLAY DATA RAM (DDRAM) ......................................................................................................... 10 CHARACTER GENERATOR ROM (CGROM)..................................................................................... 11 CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 12 LCD DRIVER CIRCUIT....................................................................................................................... 13 INSTRUCTION DESCRIPTION.................................................................................................................. 14 INITIALIZING............................................................................................................................................. 18 HARDWARE RESET .......................................................................................................................... 18 INSTRUCTION INITIALIZING WITH RESET....................................................................................... 20 LCD DRIVING POWER SUPPLY CIRCUIT................................................................................................ 22 MPU INTERFACE...................................................................................................................................... 23 INTERFACING WITH 8080-SERIES MICROPROCESSORS.............................................................. 23 INTERFACING WITH 6800-SERIES MICROPROCESSORS.............................................................. 23 APPLICATION INFORMATION FOR LCD PANEL .................................................................................... 24 FRAME FREQUENCY ............................................................................................................................... 26 MAXIMUM ABSOLUTE RATE................................................................................................................... 27 ELECTRICAL CHARACTERISTICS .......................................................................................................... 28 DC CHARACTERISTICS .................................................................................................................... 28 AC CHARACTERISTICS .................................................................................................................... 30
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
INTRODUCTION
This character driver and controller LSI for liquid crystal dot matrix display systems can display 1-line of 16 characters with the 5 x 8 dots format. It is capable of interfacing various microprocessors, supporting the 4-bit or 8-bit parallel mode. Voltage follower and bias circuit is built in the IC.
FEATURES
Driver Output Circuits - 8 common outputs / 80 segment outputs Applicable Duty Ratio Font size 5x8 Display size 1-line x 16 characters Duty 1/8 Contents of outputs 1 x 16 characters
On-chip Display Data RAM - - - - - - - - - - - - - Character Generator ROM (CGROM): 10,160 bits (254 characters x 5 x 8 dots) Character Generator RAM (CGRAM): 80 bits (2 characters x 5 x 8 dots) Display Data RAM (DDRAM): 256 bits (16 characters x 1-line + 16 extended characters) 8-bit parallel interface with 6800-series or 8080-series MPU 4-bit parallel interface with 6800-series or 8080-series MPU Simple instruction set COM / SEG bi-directional (4 types LCD application available) Hardware reset (RESETB) Internal RC oscillator circuit Voltage follower & bias circuit Automatic power on reset circuit Supply voltage (VDD): 2.4 to 5.5 V LCD driving voltage (VLCD = V0 - VSS): 6.0V Max.
Microprocessor Interface
Function Set
On-chip Analog Circuit
Operating Voltage Range
Low Power Consumption Package Type - Gold bumped chip
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
ECKON Power On Reset (POR) RESETB MI Input Buffer CSB RS RW_WR E_RD Parallel Interface 4 bit/8 bit (6800/8080 -series) Instruction Register (IR)
CK
DIRC
Oscillator
Timing Generator
8
Instruction Decoder 8 bits Shift Register Common Driver
COM1 to COM8
Address Counter 8 Data Register (DR)
Display Data RAM (DDRAM) 256 bits 5 8 8 80 bits Shift Register
DB7 to DB4 DB3 to DB0
8 Data Output Register (OR)
8 5 Character Generator ROM (CGROM) 10,160 bits 5
80 bits Latch Circuit
SEG1 to Segment SEG80 Driver
5 Busy Flag Character Generator RAM (CGRAM) 80 bits 5 GND
Cursor and Blink Controller
LCD Driving Voltage Selector
VDD Voltage Follower & Bias Resistor
Segment Data Conversion DIRS V0 V1 V2 V3 V4
Figure 1. Block Diagram
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
PAD CONFIGURATION
129
z
60
130 Y 136 137 (0,0) X
59 53 52
S6A0031
144 1
PAD DUMMY_PAD
45 44
Figure 2. S6A0031 Chip Configuration
Table 1. S6A0031 Pad Dimensions Item Chip size Pad pitch Pad No. 1 to 44 45 to 144 1 to 44 Bumped pad size 45 to 59 60 to 129 130 to 144 Bumped pad height COG Align Key Coordinate
30m 30m 30m 30m 30m 30m 30m 30m 30m 30m
Size X 5430 90 70 52 92 42 92 17 (Typ.) 92 42 92 42 Y 1410
Unit
m
1 to 144
(-2600, +605)
(+2600, +590) 60m
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates [Unit: m]
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Name
DUMMY VSS VSS VSS ECKON VDD V4 V3 V2 V1 CK VDD VDD VDD V0 V0 VDD VDD VDD RESETB RS RW_WR VSS E_RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CSB VSS MI VDD TEST VSS DIRC VDD DIRS VSS DUMMY COM1 COM2 COM3 COM4 COM5 COM6
X
-1935 -1845 -1755 -1665 -1575 -1485 -1395 -1305 -1215 -1125 -1035 -945 -855 -765 -675 -585 -495 -405 -315 -225 -135 -45 45 135 225 315 405 495 585 675 765 855 945 1035 1125 1215 1305 1395 1485 1575 1665 1755 1845 1935 2605 2605 2605 2605 2605 2605
Y
-595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -555 -485 -415 -345 -275 -205
No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Name
COM7 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 DUMMY DUMMY SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46
X
2605 2605 2605 2605 2605 2605 2605 2605 2605 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385
Y
-135 -65 5 75 145 215 285 355 425 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595
No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Name
SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 DUMMY DUMMY SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
X
-455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605
Y
595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 595 425 355 285 215 145 75 5 -65 -135 -205 -275 -345 -415 -485 -555
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description Name VDD VSS V0 I/O Supply Supply I Power supply Ground Bias voltage Input for LCD driving LCD driving voltage outputs. Voltages should have the following relationship; V1 V2 V3 V4 O V0 V1 V2 = V3 V4 VSS These voltages are generated as following table. LCD bias 1/4 bias V1 (3/4) x V0 V2 (2/4) x V0 V3 V4 (1/4) x V0 Description
SYSTEM CONTROL
Table 3. Pin Description (Continued) Name ECKON I/O I Description Clock source selection input When ECKON = "High", External clock by CK pin is used as system clock, and internal oscillator circuit is turned OFF. When ECKON = "Low", internal oscillator is used. External clock input (when ECKON = "High") It must be fixed "High" or "Low" when the internal oscillation circuit is used (When ECKON = "Low"). MPU interface selection input MI = "Low", 8080-series MPU MI = "High", 6800-series MPU COM direction selection input When DIRC = "Low" COM1 COM2 - - - - COM7 COM8 When DIRC = "High" COM8 COM7 - - - - COM2 COM1 SEG direction selection input When DIRS = "Low" SEG1 SEG2 - - - - SEG79 SEG80 When DIRS = "High" SEG80 SEG79 - - - - SEG2 SEG1
CK
I
MI
I
DIRC
I
DIRS
I
5
S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
MPU INTERFACE
Table 3. Pin Description (Continued) Name RESETB CSB I/O I I Description Reset input Initialization is performed by "Low" level sensing of the RESETB signal. Chip selection input S6A0031 is selected while CSB is "Low". Register selection input When RS = "Low", instruction register When RS = "High", data register In 8080-series MPU interface mode, this pin is connected to WR pin of MPU and is an active high write signal. In 6800-series MPU interface mode, this pin is connected to R/W pin of MPU. When RW_WR = "High", read mode When RW_WR = "Low", write mode In 8080-series MPU interface mode, this pin is connected to RD pin of MPU and is a low enable read signal. In 6800-series MPU interface mode, this pin is connected to E pin of MPU and enables read or write command according to RW_WR signal. When 8-bit interface mode, used as bi-directional data bus DB0 to DB7 During 4-bit bus mode, only DB4 to DB7 are used. In this case DB0 - DB3 pins are don' t care (connect to "High", "Low" or open).
RS
I
RW_WR
I
E_RD
I
DB0 to DB3 DB4 to DB7
I/O
LCD DRIVER OUTPUT
Table 3. Pin Description (Continued) Name COM1 to COM8 SEG1 to SEG80 I/O O O Description Common signal output for character display Segment signal output for character display
TEST
Table 3. Pin Description (Continued) Name TEST I/O I Description Test pin This pin is not used for normal operation and should be connect to "Low".
*NOTE: DUMMY - These pins should be opened (floated).
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
S6A0031 has two kinds of interface type with MPU: 4-bit bus or 8-bit bus. 4-bit bus and 8-bit bus is selected by the DL bit in the instruction register, and 6800-series MPU or 8080-series MPU is selected by MI pin. Table 4. Various Kinds of MPU Interface according to MI and DL Bit MI 6800-series (H) 8080-series (L) DL 8-bit (H) 4-bit (L) 8-bit (H) 4-bit (L) CSB CSB CSB CSB CSB RS RS RS RS RS RW_WR R/W R/W WR WR E_RD E E RD RD DB0 to DB3 DB0 to DB3 DB0 to DB3 DB4 to DB7 DB4 to DB7 DB4 to DB7 DB4 to DB7 DB4 to DB7
NOTE: "-" - Don' care ("High", "Low" or Open) t (H): fixed "High" (VDD) (L): fixed "Low" (VSS)
MI: "High" = 6800-series MPU, "Low" = 8080-series MPU DL: "High" = 8-bit mode, "Low" = 4-bit mode CSB: "High" = chip is not selected, "Low" = chip is selected RS: "High" = data register, "Low" = instruction register RW_WR: Read / Write indicating signal in 6800 mode, active high signal for writing command in 8080 mode. E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode, low enable signal for reading command in 8080 mode. Parallel Interface During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM. Target RAM is selected by RAM address set instruction. The Instruction register (IR) is used only to store instruction code transferred from MPU. To select DR or IR register, RS input pin is used. During reading operation, 8-bit output data register (OR) is used. The output data register (OR) is used as temporary data storage place for being read from DDRAM / CGRAM. Destination RAM is selected by RAM address set instruction. After RAM address set, the first reading in the 8-bit bus mode (first and second reading in the 4-bit bus mode) is a dummy cycle (figure 3, 4, 5, 6). The valid data comes from the second reading in the 8-bit bus mode (from the 3rd reading in 4-bit bus mode). The dummy cycle makes the address counter (AC) indicate the correct address. So it is recommended to set address before writing. The instruction read operation is supported for indicating internal operation is being processed (Busy Flag). In the 4-bit bus mode, it is needed to transfer 4-bit data (through DB4 to DB7) by two times. The high order bits (for 8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3) in read and write transaction. The DB0 to DB3 pins are floated in this 4-bit bus mode. After RESETB operation, S6A0031 considers the first 4-bit data from MPU as the high order bits in the 4-bit bus mode.
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
DL MI CSB RS RW_WR E_RD DB7 to DB0
Instruction W rite Busy Flag Read Dummy Data Read
Valid Data
Valid Data Read
Data W rite
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800-series MPU Mode)
DL MI CSB RS RW_WR E_RD DB7 to DB0
Instruction W rite Busy flag Read Dummy Data Read
Valid Data
Valid Data Read
Data W rite
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (8080-series MPU Mode)
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
DL MI CSB RS RW_WR E_RD DB7 to DB0
Upper 4-bit Lower 4-bit
BF
A3 A0
D7 D4
D3 D0
D7 D4
D3 D0
Instruction W rite
Busy Flag & Address Read
Dummy Data Read
Valid Data Read
Data W rite
Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (6800-series MPU Mode)
DL MI CSB RS RW_WR E_RD DB7 to DB0
Upper 4-bit Lower 4-bit
BF
A3 A0
D7 D4
D3 D0
D7 D4
D3 D0
Instruction W rite
Busy Flag & Addr ess Read
Dummy Data Read
Valid Data Read
Data W rite
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (8080-series MPU Mode) Busy Flag When DB7 is "High" in read status operation, it indicates that the internal operation is in busy status and can accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, except display clear instruction.
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
ADDRESS COUNTER (AC)
Address Counter (AC) in S6A0031 stores DDRAM / CGRAM address. After writing into or reading from DDRAM / CGRAM, AC is automatically increased or decreased by 1 according to the entry mode.
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 32 x 8 bits (16 characters + 16 extended characters). DDRAM address is set in the address counter (AC) as a hexadecimal number.
1 COM1 COM8
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
00
01
02
03
04
05
06
07
08
09
0A
0B
0C 0D 0E
0F
(a) Display shift is not performed
1 COM1 COM8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
01
02
03
04
05
06
07
08
09
0A
0B
0C 0D 0E
0F
10
(b) Display shift left is performed
1 COM1 COM8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1F
00
01
02
03
04
05
06
07
08
09
0A
0B
0C 0D 0E
(c) Display shift right is performed Figure 7. DDRAM Address
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
CHARACTER GENERATOR ROM (CGROM)
CGROM has 5 x 8-dot 254 characters. The CGROM character code 00h and 01h are CGRAM character data area. Table 5. CGROM Character Code (00)
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
CHARACTER GENERATOR RAM (CGRAM)
CGRAM has up to 5 x 8-dot 2 characters. By writing font data to CGRAM, user defined character can be used. Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0 CGRAM address A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CGRAM data P7 P6 P5 P4 P3 P2 P1 P0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pattern number
00000000 (00h)
Pattern 1
00000001 (01h)
Pattern 2
NOTE: "-" - Don' care . t
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
LCD DRIVER CIRCUIT
LCD Driver circuit has 8 common and 80 segment signals for driving LCD. Data from CGRAM / CGROM are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. COM1 to COM8 have 1/8 duty ratio. SEG bi-directional function is selected by DIRS input, and COM shift direction is selected by DIRC input. Table 7. SEG Data Shift Direction DIRS pin Low High SEG data shift direction SEG1 SEG2 SEG3 - - - - - - - SEG78 SEG79 SEG80 SEG80 SEG79 SEG78 - - - - - - - SEG3 SEG2 SEG1
Table 8. COM Data Shift Direction DIRC pin Low High COM data shift direction COM1 COM2 COM3 - - - - - - - - COM6 COM7 COM8 COM8 COM7 COM6 - - - - - - - - COM3 COM2 COM1
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PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 9. Instruction Table Instruction *Clear display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 1
Description Write "20H" to DDRAM and set DDRAM address to "00H" from AC DDRAM address is set to 00h from AC and the cursor returns to 00h position. The contents of DDRAM are not changed. Assign cursor moving direction and enable the shift of entire display Set display (D), cursor (C), and blinking of cursor (B) ON / OFF control Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data Set interface data length (DL: 4-bit / 8-bit) instruction Set CGRAM address in address counter. Set DDRAM address in address counter. Whether in internal operation or not can be known by reading BF, The contents of address counter can also be read Write data into DDRAM / CGRAM Read data from DDRAM / CGRAM
Return home
0
0
0
0
0
0
0
0
1
-
Entry mode set
0
0 0
0 0
0 0
0 0
0 0
0 1
1 D
I/D C
SH B
Display ON / OFF 0 control Cursor or display shift Function set CGRAM address set DDRAM address set Read busy flag and address Write data Read data
("-": Don' care) t 0
0
0
0
0
1
S/C R/L
-
-
0 0 0
0 0 0
0 0 1
0 1 0
1 0 0
DL 0 A4
A3 A3
A2 A2
A1 A1
A0 A0
0 1 1
1 0 1
BF D7 D7
D6 D6
D5 D5
A4 D4 D4
A3 D3 D3
A2 D2 D2
A1 D1 D1
A0 D0 D0
NOTES 1. Instruction execution time depends on the internal process time of S6A0031, therefore it is necessary to provide a time larger than one MPU interface cycle time (tc) between execution of two successive instructions. 2. "Clear Display" instruction has 850s execution time (when fosc = 40.0kHz), so check the Busy flag or wait for more than 850s after using "Clear Display" instruction.
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 1 Clear all the display data by writing "20H" (space code of CGROM) to all the DDRAM address, and set the DDRAM address to "00H" into AC (address counter). For this instruction, the CGROM address "20H" have to set space code. If the display position has shifted then it returns to the original positions. Namely, when display data is shifted and cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. It makes entry mode to increment (I/D = "High"). Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 1 Return Home instruction field makes cursor return home. DDRAM address is set to 00h from AC and the cursor returns to 00h position. The contents of DDRAM are not changed. Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 I/D DB0 SH
0 0 0 0 0 0 0 1 Set the moving direction of cursor and display after data writing or reading instruction.
I/D: Increment / Decrement of DDRAM / CGRAM Address (Cursor or Blink) After DDRAM / CGRAM data write/read operation, DDRAM / CGRAM address is increased (I/D = "High") or decreased (I/D = "Low") by1. So in case of DDRAM data transfer operation and cursor or blink is turned on, cursor or blink moves to right (I/D = "High") or left (I/D = "Low"), but in CGRAM data transfer operation, cursor or blink does not move. SH: Shift of Entire Display When DDRAM read (CGRAM read / write) operation or SH = "Low", entire display is not shift. Only when SH = "High" and DDRAM write operation, entire display is shift according to I/D value (I/D = "1": shift left, I/D = "0": shift right). Display ON / OFF Control RS R/W DB7 DB6 DB5 DB4 0 DB3 1 DB2 D DB1 C DB0 B
0 0 0 0 0 Control display / cursor / blink ON / OFF 1 bit register.
D: Display ON / OFF Control Bit When D = "High", entire display is turned ON. When D = "Low", entire display is turned OFF, but display data is remained in DDRAM. C: Cursor ON / OFF Control Bit When C = "High", cursor is turned ON. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B: Cursor Blink ON / OFF Control Bit When B = "High", cursor blink is ON, that performs alternate between all high data (black pattern) and display character at the cursor position. When B = "Low", blink is OFF.
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 1 S/C R/L Without writing or reading of display data, shift right/left the cursor position or display. This instruction is used to correct or search display data (refer to table 10). Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. Table 10. Shift Patterns According to S/C and R/L Bits S/C 0 0 1 1 Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/L 0 1 0 1 Operation Shift cursor to the left, AC is decreased by 1 Shift cursor to the right, AC is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
0 0 0 0 1 DL DL: Interface Data Length Control Bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. When 4-bit bus mode, it needs to transfer 4-bit data by two times. CGRAM Address Set RS R/W DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
0 0 0 1 0 0 A3 A2 A1 A0 Set CGRAM address to AC This instruction makes CGRAM data available from MPU for user defined character pattern. CGRAM address is from 00h to 0Fh. DDRAM Address Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 0 0 A4 A3 A2 A1 A0 Set DDRAM address to AC Before writing / reading data into / from the RAM, set the address by RAM Address Set instruction. Next, when data are written/read in succession, the address is automatically increased by 1 (when I/D = "High") or decreased by 1 (when I/D = "Low"). The address ranges are 00h to 1Fh.
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
Read Busy Flag and Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 BF A4 A3 A2 A1 A0 This instruction shows whether S6A0031 is in internal operation or not. If the resultant BF is "High", it means the internal operation is in progress and you have to wait until BF to be "Low", and then the next instruction can be performed. In this instruction you can read also the value of address counter. Write Data RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write binary 8- / 5- bit data to DDRAM / CGRAM The selection of RAM from DDRAM / CGRAM is set by the previous address set instruction (DDRAM address set, CGRAM address set). After write operation, the address is automatically increased / decreased by 1, according to the entry mode. Read Data RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read binary 8- / 5- bit data from DDRAM / CGRAM The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, and the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction: it also transfers RAM data to output data register. After read operation address counter is automatically increased / decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, after this operation, AC is increased / decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction. RAM address is dummy data, so the correct RAM data come from the second read transaction. After reading operation, the address is increased by 1 automatically.
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INITIALIZING
HARDWARE RESET
When the power is turned on, S6A0031 is initialized automatically by the power on reset circuit (refer to figure 8). In case of RESETB pin becomes "Low" and durable the state for more than 1.2s (VDD = 3V), S6A0031 can be initialized too. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High" (busy state) to the end of initialization. Display Clear All the DDRAM data is set to "20H" Return Home Address counter = "00H" Entry Mode Set Instruction I/D = 1: Address counter is set to increment mode. SH = 0: Entire display shift is disabled. Display ON / OFF Control Instruction C = 0: cursor OFF B = 0: blink OFF D = 0: display OFF Function Set Instruction DL = 1: 8-bit interface mode CGRAM / DDRAM Address RAM address counter is set to "00H".
tRDD VDD
0.9VDD 0.1VDD 0.1VDD
tOFF
0.1VDD
VDD Rising Time Power Off Time Note:
tRDD tOFF
1 ms 1 ms
If the upper power conditions are not satisfied in power on/off sequence, the internal power on reset (POR) circuit will not operates normally.
Figure 8. Power ON / OFF Timing
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
tRW RESETB Internal Reset Time
Reset Pulse Width Reset Time Note:
tR
tRW tR
1.2 s 850 s
tRW indicates the minimum RESETB duration for activate internal reset signal tR indicates reset completion time of internal circuit from the start of the internal reset signal (when fosc = 40.0kHz).
Figure 9. RESET Timing
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION INITIALIZING WITH RESET
8-bit Interface Mode (fosc = 40.0kHz) VDD-VSS Power ON When Using RESETB Input for Initializing Wait until Power is Stable Set Reset (RESETB Pin = "Low") Wait for more than 1.2s Release Reset (RESETB Pin = "High") Wait for more than 1ms When just Using Internal Power On Reset Circuit
Wait for more than 20ms after VDD rises to 0.9 VDD
Command Input
Function Set
RS 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DL 0 0 0 1 (1) 0 0 0 0 0 0 0 0 0 0 0 1 1 D I/D C SH B
Entry Mode Set Display ON / OFF Control
End of Initialization
RAM Address Set RAM Data Write
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
4-bit Interface Mode (fosc = 40.0kHz) VDD-VSS Power ON When Using RESETB Input for Initializing Wait until Power is Stable Set Reset (RESETB Pin = "Low") Wait for more than 1.2s Release Reset (RESETB Pin = "High") Wait for more than 1ms When just Using Internal Power On Reset Circuit
Wait for more than 20ms after VDD rises to 0.9 VDD
Command Input
Function Set
RS 0 0 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DL 0 0 0 1 (0) 0 0 0 0 0 0 0 1 0 1 0 D 0 I/D 0 C 0 SH 0 B -
Entry Mode Set
Display ON / OFF Control
End of Initialization
RAM Address Set RAM Data Write
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVING POWER SUPPLY CIRCUIT
The Power Supply circuit produces LCD panel driving voltage at low power consumption. The LCD driving Power Supply circuit consists of external voltage input and voltage follower.
VDD VDD
S6B0031
External Power Supply
V0 O P E N V1 V2 V3 V4 VSS
C1
GND * Recommended Capacitance value is 0.1 to 4.7F Figure 10. LCD Driving Power Connection
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
MPU INTERFACE
INTERFACING WITH 8080-SERIES MICROPROCESSORS
VCC
VCC A0 A1 - A7 IORQ RD WR D0 - D7 RESET GND RESETB DECODER RS CSB
VDD MI
MPU
S6A0031
E_RD RW_WR DB0 - DB7 RESETB VSS
GND
(8080-series)
GND
Figure 11. Interfacing with 8080-series MPU
INTERFACING WITH 6800-SERIES MICROPROCESSORS
VCC VCC MI
VCC A0 A1 - A7 VMA E R/W D0 - D7 RESET GND RESETB DECODER RS CSB
VDD
MPU
S6A0031
E_RD RW_WR DB0 - DB7 RESETB VSS
(6800 -series)
GND
Figure 12. Interfacing with 6800-series MPU
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
APPLICATION INFORMATION FOR LCD PANEL
Chip Bottom & Lower View (DIRC = "0", DIRS = "0")
SEG80 SEG79 SEG78 SEG77 SEG76 * * * * * * * * * * * * * SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM8 COM7 COM6 *** COM2 COM1
BOTTOM VIEW
Figure 13. Chip Bottom & Lower View Interfacing with LCD Panel Chip Bottom & Upper View (DIRC = "1", DIRS = "1")
BOTTOM VIEW
SEG1 SEG2 SEG3 SEG4 SEG5 * * * * * * * * * * * * * SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
COM1 COM2 *** COM6 COM7 COM8
Figure 14. Chip Bottom & Upper View Interfacing with LCD Panel
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
Chip Top & Lower View (DIRC = "0", DIRS = "1")
Figure 15. Chip Top & Lower View Interfacing with LCD Panel Chip Top & Upper View (DIRC = "1", DIRS = "0")
SEG1 SEG2 SEG3 SEG4 SEG5 * * * * * * * * * * * * * SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
TOP VIEW
COM8 COM7 COM6 *** COM2 COM1
COM1 COM2 *** COM6 COM7 COM8
TOP VIEW
SEG80 SEG79 SEG78 SEG77 SEG76 * * * * * * * * * * * * * SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
Figure 16. Chip Top & Upper View Interfacing with LCD Panel
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
FRAME FREQUENCY
1-line selection period
12
----
7812
----
7812
----
7812
----
78
V0 V1 COM1 V4 VSS
1 FRAME 1 FRAME
1-line Selection Period = 16 Clock Pulses x 4 Division One Frame = 64 x 8 x 25.0s = 12.8ms (1 Clock = 25.0s at fosc = 40.0kHz) Frame Frequency = 1 / 12.8ms = 78Hz
Figure 17. Frame Frequency
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
MAXIMUM ABSOLUTE RATE
Table 11. Maximum Absolute Rate Characteristics Power supply voltage (1) Power supply voltage (2) Input voltage Operating temperature Storage temperature Symbol VDD V0 VIN TOPR TSTG Value -0.3 to +7.0 -0.3 to + 8.0 -0.3 to VDD +0.3 -30 to +85 -55 to +125 Unit V V V C C
NOTE: 1. All the voltage levels are based on VSS = 0V. 2. Voltage greater than above may damage the circuit. Voltage level: V0 VDD VSS Voltage level: V0 V1 V2 = V3 V4 VSS
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Table 12. DC Characteristics (VDD = 2.4V to 3.6V, Ta = -30 to +85 oC) Item Operating voltage Symbol VDD IDD1 Condition Display operation V0 = 6V without load No access from MPU Access operation from MPU fcyc = 200kHz VIN = 0V to VDD Io = 50A Io = 50A VDD = 3V, Ta = 25 oC VLCD = V0 - VSS Min. 2.4 Typ. Max. 3.6 50 A 0.7VDD VSS -1 55 3.0 78 40.0 500 VDD V 0.3VDD 1 5 k 10 101 6.0 Hz kHz V A Unit V
Supply current (VDD = 3V, Ta = 25 oC)
IDD2 Input voltage Input leakage current RON resistance Frame frequency External clock frequency LCD driving voltage VIH VIL ILEAK RCOM RSEG f FR f CK VLCD
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
Table 12. DC Characteristics (Continued) (VDD = 3.6V to 5.5V, Ta = -30 to +85 oC) Item Operating voltage Symbol VDD IDD1 Condition Display operation V0 = 6V without load No access from MPU Access operation from MPU fcyc = 200kHz VIN = 0V to VDD Io = 50A Io = 50A VDD = 3V, Ta = 25 oC VLCD = V0 - VSS Min. 3.6 Typ. Max. 5.5 80 A 0.7VDD VSS -1 55 3.6 78 40.0 1000 VDD V 0.3VDD 1 5 k 10 101 6.0 Hz kHz V A Unit V
Supply current (VDD = 5V, Ta = 25 oC)
IDD2 Input voltage Input leakage current RON resistance Frame frequency External clock frequency LCD driving voltage VIH VIL ILEAK RCOM RSEG f FR f CK VLCD
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
6800-Series MPU Interface & Write Instruction Table 13. AC Characteristics (6800-series Write Instruction) Condition Characteristic E cycle time Pulse rise / fall time E pulse width high VDD = 2.4V to 3.6V, Ta = -30 to +85 oC E pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time E cycle time Pulse rise / fall time E pulse width high VDD = 3.6V to 5.5V, Ta = -30 to +85 oC E pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time Symbol tC tR , tF tWH tWL tSU1 tH1 tSU2 tH2 tC tR , tF tWH tWL tSU1 tH1 tSU2 tH2 Min. 650 450 150 60 30 100 50 350 250 100 40 10 40 10 Typ. Max. 25 25 ns ns Unit
RS, CSB tSU1 RW_WR tWH tF E_RD tR DB0 to DB7 tC Figure 18. Write Bus Mode Timing (6800-series MPU Interface) tSU2 tH2 tWL tH1
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
8080-series MPU Interface & Write Instruction Table 14. AC Characteristics (8080-series Write Instruction) Condition Characteristic WR cycle time Pulse rise / fall time WR pulse width high VDD = 2.4V to 3.6V, Ta = -30 to +85 oC WR pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time WR cycle time Pulse rise / fall time WR pulse width high VDD = 3.6V to 5.5V, Ta = -30 to +85 oC WR pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time Symbol tC tR , tF tWH tWL tSU1 tH1 tSU2 tH2 tC tR , tF tWH tWL tSU1 tH1 tSU2 tH2 Min. 650 150 450 60 30 100 50 350 100 250 40 10 40 10 Typ. Max. 25 25 ns ns Unit
RS, CSB tSU1 RW_WR tF DB0 to DB7 tC Figure 19. Write Bus Mode Timing (8080-series MPU Interface) tSU2 tH2 tWL tR tH1 tWH
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S6A0031
PRELIMINARY SPEC. VER. 0.5
8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
6800-series MPU Interface & Read Instruction Table 15. AC Characteristics (6800-series Read Instruction) Condition Characteristic E cycle time Pulse rise / fall time E pulse width high VDD = 2.4V to 3.6V, Ta = -30 to +85 oC E pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time E cycle time Pulse rise / fall time E pulse width high VDD = 3.6V to 5.5V, Ta = -30 to +85 oC E pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time Symbol tC tR , tF tWH tWL tSU tH tD tDH tC tR , tF tWH tWL tSU tH tD tDH Min. 650 450 150 60 30 20 350 250 100 40 10 10 Typ. Max. 25 360 25 120 ns ns Unit
RS, CSB tSU RW_WR B E_RD tR DB0 to DB7 tC Figure 20. Read Bus Mode Timing (6800-series MPU Interface) tD tDH tWH tF tWL tH
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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.5
S6A0031
8080-series MPU Interface & Read Instruction Table 16. AC Characteristics (8080-series read instruction) Condition Characteristic RD cycle time Pulse rise / fall time RD pulse width high VDD = 2.4V to 3.6V, Ta = -30 to +85 oC RD pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time RD cycle time Pulse rise / fall time RD pulse width high VDD = 3.6V to 5.5V, Ta = -30 to +85 oC RD pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time Symbol tC tR , tF tWH tWL tSU tH tD tDH tC tR , tF tWH tWL tSU tH tD tDH 20 350 100 250 40 10 10 Min. 650 150 450 60 30 Typ. Max. 25 360 25 120 ns ns Unit
RS, CSB tSU E_RD tF DB0 to DB7 tC tD tDH tWL tR tH tWH
Figure 21. Read Bus Mode Timing (8080-series MPU Interface)
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